1. Field of the Invention
This invention relates to semiconductor devices and its manufacturing method, and, more specifically, to the formation of buried layers in such devices.
2. Description of Related Art
It is well known in semiconductor processing that the minimization of the number of masking operations in fabricating a semiconductor device is a constant goal. Thus processes which can eliminate a masking operation are highly desirable in the semiconductor processing art.
Fabrication of complementary vertical bipolar devices for analog signal processing on a single integrated circuit with N type and P type buried layers are known in the art. For example, Rupit Patel et al, “a 30V Complementary Bipolar Technology on SOI for High Speed Precision Analog Circuits,” IEEE BCTM, pp. 48–50, 1997, and M. C. Wilson et al, “Process HJ: A 30 GHz NPN and 20 GHz PNP Complementary Bipolar Process for High Linearity RF Circuits,” IEEE BCTM, pp. 164–167, 1998, describe examples of these types of circuits. In both publications the circuits taught use both N type and P type buried layers which are formed using separate mask and implant steps to form each buried layer. This requires two masks and two implants to form the two buried layers.